Process Engineer, Wafer Preparation & Assembly (Starlink/Akoustis)

Job description

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. PROCESS ENGINEER, WAFER PREPARATION & ASSEMBLY (STARLINK/AKOUSTIS) Akoustis is now operating as a wholly owned subsidiary of SpaceX providing industry leading RF filters using patented XBAW technology to help drive the mission of making human life multi-planetary, while also connecting the world through Starlink. Our work helps further the impact that Starlink is already making on millions of users around the world, while allowing us to broaden that reach dramatically and continue connecting the unconnected here on earth. We are looking for a hands-on Process Engineer to develop, optimize, qualify, and implement the full wafer-to-die preparation flow: wafer thinning and backside processing, dicing, die cleaning and handling, laser marking, inspection, and final package singulation. You will work directly with equipment and cross-functional partners (package engineering, assembly, test, reliability, quality, and external manufacturers) to deliver high-quality die that support downstream yield and reliability. RESPONSIBILITIES Develop and qualify wafer back-grinding, thinning, stress-relief, and backside finishing processes; set thickness, TTV, bow, warp, and roughness targets while minimizing chipping, cracking, subsurface damage, and edge defects Develop and optimize mechanical wafer dicing (including thin wafers and difficult materials such as SiC); select blades, tapes, and parameters (speed, feed, depth, coolant, dressing, single- or multi-pass) and control chipping, sidewall quality, delamination, and street/exclusion requirements Establish post-dice die cleaning, drying, handling, tape mount/release (UV and non-UV), pick, sort, and presentation methods that protect die integrity, orientation, and traceability for flip-chip, wire-bond, and other assembly flows Develop and qualify laser marking processes for wafers and bare die (including green/UV sources); optimize mark contrast and resolution while avoiding damage to electrical performance, metallization, passivation, or mechanical integrity, and implement vision/OCR verification Develop final package singulation (saw, laser, or mechanical) for organic, mold, ceramic, and metal structures; minimize cracking, chipping, delamination, burrs, and edge defects and confirm impact on warpage, electrical performance, and reliability Run DOEs, define process windows and controls, troubleshoot defects, qualify equipment and consumables, incorporate supplier and production feedback, and transfer robust processes into manufacturing BASIC QUALIFICATIONS Bachelor's degree in chemical engineering, materials science, mechanical engineering, or other engineering discipline 2+ years of hands-on experience in semiconductor wafer processing, thinning, dicing, die preparation, or manufacturing (Internship or extracurricular experience is applicable) PREFERRED SKILLS AND EXPERIENCE 3+ years of hands-on semiconductor manufacturing experience, including wafer back-grinding/thinning (including ≤150 µm wafers) and mechanical dicing/blade selection Experienced in operating and developing processes on semiconductor equipment, plus solid understanding of wafer and die handling, process troubleshooting, and statistical process control Experience with SiC or other hard materials, dicing tapes, blade dressing, two-step or partial-depth cutting, thin-film wafers, and die pick/handling equipment Laser marking of wafers or die (green, UV, or similar) and machine-vision/OCR mark verification. Package singulation and understanding of warpage, stress, cracking, chipping, and delamination mechanisms DOE, SPC, Cp/Cpk, FMEA, or Six Sigma; data analysis with JMP, Minitab, MATLAB, or Python. Equipment qualification, process transfer, OSAT/external partner support, and familiarity with JEDEC, SEMI, or IPC standards CAD familiarity (AutoCAD or SolidWorks) is a plus ADDITIONAL REQUIREMENTS Onsite in Bastrop, TX (not remote or hybrid) Up to 20% domestic and international travel for supplier and manufacturing support Willingness to work extended hours or weekends to support key milestones Ability to work in a semiconductor manufacturing environment, follow safety and cleanroom requirements, and perform light physical tasks (including lifting up to 25 lbs and handling wafers, substrates, packages, and tooling) Strong written and verbal communication skills with engineering, manufacturing, suppliers, and management ITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here . SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status. Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com .